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general description the max6953 is a compact cathode-row display driver that interfaces microprocessors to 5 ? 7 dot-matrix led displays through an i 2 c-compatible serial interface. the max6953 drives up to four digits (140 leds). included on-chip are an ascii 104-character font, mul- tiplex scan circuitry, column and row drivers, and static ram that stores each digit, as well as font data for 24 user-definable characters. the segment current for the leds is set by an internal digit-by-digit digital bright- ness control. the device includes a low-power shutdown mode, seg- ment blinking (synchronized across multiple drivers, if desired), and a test mode that forces all leds on. the led drivers are slew-rate limited to reduce emi. for an spi-compatible version, refer to the max6952 data sheet. an ev kit is available for the max6952. applications message boards medical equipment industrial displays audio/video equipment gaming machines features ? 400kbps 2-wire interface compatible with i 2 c ? 2.7v to 5.5v operation ? drives 4 monocolor or 2 bicolor cathode-row 5 ? 7 matrix displays ? built-in ascii 104-character font ? 24 user-definable characters available ? automatic blinking control for each segment ? 70? low-power shutdown (data retained) ? 16-step digital brightness control ? display blanked on power-up ? slew-rate-limited segment drivers for lower emi ? 36-pin ssop and 40-pin dip packages ? extended temperature range as standard max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ________________________________________________________________ maxim integrated products 1 ordering information digit 1 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 digit 0 o0 o1 o2 o3 o4 o5 o6 o14 o15 o16 o17 o18 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 o0 o1 o2 o3 o4 o5 o6 o19 o20 o21 o22 o23 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 digit 3 o7 o8 o9 o10 o11 o12 o13 o19 o20 o21 o22 o23 digit 2 3.3v 100nf 47 f o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 iset osc v+ v+ gnd gnd blink v+ gnd sda scl ad1 26pf c set 53.6k ? r set max6953 ad0 3.3v 4.7k ? 4.7k ? 4.7k ? t ypical application circuit 19-2312; rev 3; 3/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max6953eax -40? to +85? 36 ssop max6953epl -40? to +85? 40 pdip i 2 c is a trademark of philips corp. spi is a trademark of motorola, inc. pin configurations appear at end of data sheet.
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (typical operating circuit, v+ = 3.0v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +6v all other pins................................................-0.3v to (v+ + 0.3v) o0?13 sink current ....................................................... 500ma o14?23 source current .................................................. 50ma continuous power dissipation (t a = +70?) 36-pin ssop (derate 11.8mw/? above +70?) .....941.2mw 40-pin pdip (derate 16.7mw/? above +70?)........1333mw operating temperature range max6953e ......................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating supply voltage v+ 2.7 5.5 v t a = t min to t max 130 shutdown supply current i shdn shutdown mode, all digital inputs at v+ or gnd t a = +25? 70 100 ? operating supply current i+ all segments on, intensity set to full, internal oscillator, no display load connected, blink open circuit 12 15 ma master clock frequency (osc internal oscillator) f osc osc = rc oscillator, r set = 53.6k ? , c set = 26pf 4 mhz master clock frequency (osc external clock) f osc osc overdriven externally 1 8 mhz dead clock protection frequency f osc 90 khz osc internal/external detection threshold v osc 1.7 v osc high time t ch 50 ns osc low time t cl 50 ns slow segment blink period (osc internal oscillator) f slowblink osc = rc oscillator, r set = 53.6k ? , c set = 26pf 1s fast segment blink period (osc internal oscillator) f fastblink osc = rc oscillator, r set = 53.6k ? , c set = 26pf 0.5 s fast or slow segment blink duty cycle (note 2) 49.5 50.5 % column drive source current i column v led = 2.4v, v+ = 3.0v, t a = +25 o c -32 -58 ma
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (typical operating circuit, v+ = 3.0v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units segment current slew rate ? i seg / ? tt a = +25 o c 12.5 ma/? segment drive current matching (within ic) ? i seg t a = +25? 4 % logic inputs input high voltage sda, scl, ad0, ad1 v ih 0.7 x v+ v input low voltage sda, scl, ad0, ad1 v il 0.3 ? v+ v input hysteresis sda, scl, ad0, ad1 v hyst 0.05 ? v+ v input leakage current i il , i ih -2 2 a input capacitance c i 10 pf digital output sda output low voltage v olsda i sink = 4ma 0.4 v blink output low voltage v olbk i sink = 1.6ma 0.4 v max6953 timing characteristics (v+ = 2.7v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 3) 0.9 ? data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.6 ? rise time of both sda and scl signals, receiving t r (notes 2, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 2, 4) 20 + 0.1c b 300 ns
t ypical operating characteristics (typical application circuit, v+ = 3.3v, led forward voltage = 2.4v, scan limit set to 4 digits, t a = +25?, unless otherwise noted.) max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 4 _______________________________________________________________________________________ max6953 timing characteristics (continued) (v+ = 2.7v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units fall time of sda transmitting t f (notes 2, 5) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 6) 0 50 ns capacitive load for each bus line c b (note 2) 400 pf note 1: all parameters tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: guaranteed by design. note 3: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) in order to bridge the undefined region of scl? falling edge. note 4: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 5: i sink 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 6: input filters on the sda and scl inputs suppress noise spikes less than 50ns. 3.80 3.90 4.10 4.00 4.20 4.30 -40 0 -20 20 40 60 80 internal oscillator frequency vs. temperature max6953 toc01 temperature ( c) oscillator frequency (mhz) v+ = 3.3v v+ = 2.7v v+ = 5v internal oscillator frequency vs. supply voltage max6953 toc02 supply voltage (v) oscillator frequency (mhz) 4.5 3.5 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 3.6 2.5 5.5 0 0.5 1.5 1.0 2.0 2.5 0 400 200 600 800 internal oscillator waveform at osc (pin 19 or 21) max6953 toc03 timeline (ns) voltage at osc (v)
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 5 80 85 95 90 100 105 2.5 3.5 3.0 4.0 4.5 5.0 5.5 dead clock oscillator frequency vs. supply voltage max6953 toc04 supply voltage (v) oscillator frequency (khz) 0.95 0.97 0.96 0.99 0.98 1.00 1.01 2.5 3.5 4.0 3.0 4.5 5.0 5.5 output source current vs. supply voltage max6953 toc05 supply voltage (v) current normalized to 40ma waveforms at o2 (pin 3) and o14 (pin 28) v+ = 3.3v, 8/16 intensity ground for anode (pin 014) max6953 toc06 ground for cathode (pin 03) 200 s/div t ypical operating characteristics (continued) (typical application circuit, v+ = 3.3v, led forward voltage = 2.4v, scan limit set to 4 digits, t a = +25?, unless otherwise noted.) pin description pin ssop pdip name function 1, 2, 3, 6?4, 23, 24 1, 2, 3, 7?5, 26, 27 o0 to o13 led cathode drivers. o0 to o13 outputs sink current from the display? cathode rows. 4, 5, 17 4, 5, 6, 19 gnd ground 15 17 iset segment current setting. connect iset to gnd through series resistor r set to set the peak current. 16 18 ad1 address input 1. sets device slave address. connect to either gnd, v+, scl, sda to give four logic combinations. see table 3. 16, 25 n.c. not connected 18 20 blink blink output. output is open drain. 19 21 osc multiplex clock input. to use internal oscillator, connect capacitor c set from osc to gnd. to use external clock, drive osc with a 1mhz to 8mhz cmos clock. 20 22 ad0 address input 0. sets device slave address. connect to either gnd, v+, scl, sda to give four logic combinations. see table 3. 21 23 sda i 2 c-compatible serial data i/o 22 24 scl i 2 c-compatible serial clock input 25?1, 34, 35, 36 28?4, 38, 39, 40 o14 to o23 led anode drivers. o14 to o23 outputs source current to the display? anode columns. 32, 33 35, 36, 37 v+ positive supply voltage. bypass v+ to gnd with a 47? bulk capacitor and a 0.1? ceramic capacitor.
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 6 _______________________________________________________________________________________ digit o0?6 o7?13 o14?18 o19-?23 1 digit 0 rows (cathodes) r1 to r7 digit 1 rows (cathodes) r1 to r7 digit 0 columns (anodes) c1 to c5 digit 1 columns (anodes) c6 to c10 2 digit 2 rows (cathodes) r1 to r7 digit 3 rows (cathodes) r1 to r7 digit 2 columns (anodes) c1 to c5 digit 3 columns (anodes) c6 to c10 table 1. connection scheme for four monocolor digits digit o0?6 o7?13 o14?23 digit 0 columns (anodes) c1 to c10 1 digit 0 rows (cathodes) r1 to r14 - the 5 green anodes - - the 5 red anodes - digit 1 columns (anodes) c1 to c10 2 digit 1 rows (cathodes) r1 to r14 - the 5 green columns - - the 5 red anodes - table 2. connection scheme for two bicolor digits detailed description the max6953 is a serially interfaced display driver that can drive four digits of 5 ? 7 cathode-row dot-matrix dis- plays. the max6953 can drive either four monocolor digits (table 1) or two bicolor digits (table 2). the max6953 includes a 128-character font map compris- ing 104 predefined characters and 24 user-definable characters. the predefined characters follow the arial font, with the addition of the following common symbols: ? <, ? ? ? ? , and . the 24 user-definable charac- ters are uploaded by the user into on-chip ram through the serial interface and are lost when the device is pow- ered down. figure 1 is the max6953 functional diagram. serial interface serial addressing the max6953 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the max6953, and generates the scl clock that synchronizes the data transfer (figure 2). the max6953 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on the sda. the max6953 scl line oper- ates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master sys- tem has an open-drain scl output. each transmission consists of a start condition (figure 3) sent by a master, followed by the max6953 7-bit slave address plus r/ w bit (figure 6), a register address byte, 1 or more data bytes, and finally a stop condition (figure 3). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning the sda from low to high while scl is high. the bus is then free for another transmission (figure 3). iset osc blink scl sda ad0 ad1 serial interface ram blink speed select configuration registers character generator rom character generator ram current source divider/ counter network row multiplexer pwm brightness control led drivers o0 to o23 figure 1. max6953 functional diagram
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 7 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable while scl is high (figure 4). acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data (figure 5). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is sta- ble low during the high period of the clock pulse. when the master is transmitting to the max6953, the max6953 generates the acknowledge bit because the max6953 is the recipient. when the max6953 is trans- mitting to the master, the master generates the acknowledge bit because the master is the recipient. slave address the max6953 has a 7-bit-long slave address (figure 6). the eighth bit following the 7-bit slave address is the r/ w bit. it is low for a write command, high for a read command. the first 3 bits (msbs) of the max6953 slave address are always 101. slave address bits a3, a2, a1, and a0 are selected by the address input pins ad1 and ad0. these two input pins may be connected to gnd, v+, sda, or scl. the max6953 has 16 possible slave addresses (table 3) and therefore a maximum of 16 max6953 devices may share the same interface. message format for writing a write to the max6953 comprises the transmission of the max6953's slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte, which deter- mines which register of the max6953 is to be written by the next byte, if received. if a stop condition is detect- ed after the command byte is received, then the max6953 takes no further action (figure 7) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max6953 selected by the command byte (figure 8). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent max6953 internal registers because the command byte address generally autoincrements (table 4) (figure 9). message format for reading the max6953 is read using the max6953's internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for a write. the pointer generally autoincre- ments after each data byte is read using the same rules as for a write (table 4). thus, a read is initiated by first configuring the max6953's command byte by perform- ing a write (figure 7). the master can now read n con- secutive bytes from the max6953, with the first data byte being read from the register addressed by the ini- tialized command byte (figure 9). when performing stop condition start condition t buf t su , sto t hd , sta repeated start condition t su , sta t hd , dat t su , dat t low sda scl t high start condition t hd , sta t r t f figure 2. 2-wire serial interface timing details
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 8 _______________________________________________________________________________________ sda scl start msb 1 0 1 a3 a2 a1 a0 r/w lsb ack figure 6. slave address sda scl s start condition stop condition p figure 3. start and stop conditions data line stable, data valid change of data allowed sda scl figure 4. bit transfer start condition 1 scl sda by transmitter sda by receiver s 2 8 9 clock pulse for acknowledgment figure 5. acknowledge
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 9 read-after-write verification, reset the command byte's address because the stored byte address generally is autoincremented after the write (table 4). operation with multiple masters if the max6953 is operated on a 2-wire interface with multiple masters, a master reading the max6953 should use a repeated start between the write, which sets the max6953's address pointer, and the read(s) that takes the data from the location(s). this is because it is possible for master 2 to take over the bus after master 1 has set up the max6953's address pointer but before master 1 has read the data. if master 2 subse- quently changes the max6953's address pointer, then master 1's delayed read may be from an unexpected location. command address autoincrementing address autoincrementing allows the max6953 to be configured with the shortest number of transmissions by minimizing the number of times the command byte needs to be sent. the command address or the font pointer address stored in the max6953 generally incre- ments after each data byte is written or read (table 4). digit registers the max6953 uses eight digit registers to store the char- acters that the user wishes to display on the four 5 ? 7 led digits. these digit registers are implemented with two planes of 4 bytes, called p0 and p1. each led digit is represented by 2 bytes of memory, 1 byte in plane p0 and the other in plane p1. the digit registers are mapped so that a digit? data can be updated in plane p0, or plane p1, or both planes at the same time (table 5). if the blink function is disabled through the blink enable bit e (table 10) in the configuration register, then the digit register data in plane p0 is used to multiplex the display. the digit register data in p1 is not used. if the blink function is enabled, then the digit register data in both plane p0 and plane p1 are alternately used to mul- tiplex the display. blinking is achieved by multiplexing the led display using data planes p0 and p1 on alter- nate phases of the blink clock (table 11). the data in the digit registers does not control the digit segments directly. instead, the register data is used to address a character generator, which stores the data of a 128-character font (table 15). the lower 7 bits of the digit data (d6 to d0) select the character from the font. the most-significant bit of the register data (d7) selects whether the font data is used directly (d7 = 0) or whether the font data is inverted (d7 = 1). the inversion feature can be used to enhance the appearance of bicolor displays by displaying, for example, a red char- acter on a green background. display blink mode the display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes p0 and p1. if the digit register data for any digit is different in the two planes, then that sa ap 0 slave address command byte acknowledge from max6953 r/w acknowledge from max6953 d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition figure 7. command byte received aa ap 0 slave address command byte data byte acknowledge from max6953 r/w 1 byte autoincrement memory word address acknowledge from max6953 acknowledge from max6953 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into max6953's registers s figure 8. command and single data byte received
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 10 ______________________________________________________________________________________ pin device address ad1 ad0 a6 a5 a4 a3 a2 a1 a0 gnd gnd 1 01000 0 gnd v+ 1 01000 1 gnd sda 1 01001 0 gnd scl 1 01001 1 v+ gnd 1 01010 0 v+ v+ 1 01010 1 v+ sda 1 01011 0 v+ scl 1 01011 1 sda gnd 1 01100 0 sda v+ 1 01100 1 sda sda 1 01101 0 sda scl 1 01101 1 scl gnd 1 01110 0 scl v+ 1 01110 1 scl sda 1 01111 0 scl scl 1 01111 1 table 3. max6953 address map s aaap 0 slave address command byte data byte acknowledge from max6953 r/w n bytes autoincrement memory word address acknowledge from max6953 acknowledge from max6953 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how command byte and data byte map into max6953's registers figure 9. n data bytes received digit appears to flip between two characters. to make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. once blinking has been configured, it con- tinues automatically without further intervention. blink speed the blink speed is determined by frequency of the mul- tiplex clock, osc, and by setting the blink rate selection bit b (table 9) in the configuration register. the blink rate selection bit b sets either fast or slow blink speed for the whole display. initial power-up on initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (table 6). configuration register the configuration register is used to enter and exit shut- down, select the blink rate, globally enable and disable the blink function, globally clear the digit data, and reset the blink timing (table 7). shutdown mode (s data bit d0) format the s bit in the configuration register selects shutdown or normal operation. the display driver can be pro- grammed while in shutdown mode, and shutdown mode is overridden when in the display test mode. for normal operation, the s bit should be set to 1 (table 8). blink rate selection (b data bit d2) format the b bit in the configuration register selects the blink rate. this is the speed that the segments alternate between plane p0 and plane p1 refresh data. the blink rate is determined by the frequency of the multiplex clock osc, in addition to the setting of the b bit (table 9).
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 11 command address hex code register d15 d14 d13 d12 d11 d10 d9 d8 no-op x 0 0 0 0 0 0 0 0x00 intensity10 x 0 0 0 0 0 0 1 0x01 intensity32 x 0 0 0 0 0 1 0 0x02 scan limit x 0 0 0 0 0 1 1 0x03 configuration x 0 0 0 0 1 0 0 0x04 user-defined fonts x 0 0 0 0 1 0 1 0x05 factory reserved. do not write to this. x 0 0 0 0 1 1 0 0x06 display test x 0 0 0 0 1 1 1 0x07 digit 0 plane p0 x 0 1 0 0 0 0 0 0x20 digit 1 plane p0 x 0 1 0 0 0 0 1 0x21 digit 2 plane p0 x 0 1 0 0 0 1 0 0x22 digit 3 plane p0 x 0 1 0 0 0 1 1 0x23 digit 0 plane p1 x 1 0 0 0 0 0 0 0x40 digit 1 plane p1 x 1 0 0 0 0 0 1 0x41 digit 2 plane p1 x 1 0 0 0 0 1 0 0x42 digit 3 plane p1 x 1 0 0 0 0 1 1 0x43 write digit 0 planes p0 and p1 with same data (reads as 0x00) x1 10 00 00 0x60 write digit 1 planes p0 and p1 with same data (reads as 0x00) x1 10 00 01 0x61 write digit 2 planes p0 and p1 with same data (reads as 0x00) x1 10 00 10 0x62 write digit 3 planes p0 and p1 with same data (reads as 0x00) x1 10 00 11 0x63 table 5. register address map command byte address range autoincrement behavior x0000000 to x0000100 command byte address autoincrements after byte read or written. x0000101 command byte address remains at x0000101 after byte read or written, but the font address pointer autoincrements. x0000110 factory reserved; do not write to this register. x000111 to x1111110 command byte address autoincrements after byte read or written. x1111111 command byte address remains at x1111111 after byte read or written. table 4. command address autoincrement rules
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 12 ______________________________________________________________________________________ register data mode d7 d6 d5 d4 d3 d2 d1 d0 slow blinking (segments are refreshed using plane p0 for 1s, plane p1 for 1s, for osc = 4mhz). pxrte0xs fast blinking (segments are refreshed using plane p0 for 0.5s, plane p1 for 0.5s, for osc = 4mhz). pxrte1xs table 9. blink rate selection (b data bit d2) format register data d7 d6 d5 d4 d3 d2 d1 d0 configuration register p x r t e b x s table 7. configuration register format register data mode d7 d6 d5 d4 d3 d2 d1 d0 shutdown mode p x r t e b x 0 normal operation p x r t e b x 1 table 8. shutdown control (s data bit d0) format register data register power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 intensity10 1/16 (min on) 0x01 0 0 000000 intensity32 1/16 (min on) 0x02 0 0 000000 scan limit display 4 digits: 0 1 2 3 0x03 x x xxxxx1 configuration shutdown enabled, blink speed is slow, blink disabled 0x04 0 x 0000x0 user-defined font address pointer address 0x80; pointing to the first user-defined font location 0x05 1 0 000000 display test normal operation 0x07 x x xxxxx0 digit 0 plane p0 blank digit (0x20) 0x20 0 0 100000 digit 1 plane p0 blank digit (0x20) 0x21 0 0 100000 digit 2 plane p0 blank digit (0x20) 0x22 0 0 100000 digit 3 plane p0 blank digit (0x20) 0x23 0 0 100000 digit 0 plane p1 blank digit (0x20) 0x40 0 0 100000 digit 1 plane p1 blank digit (0x20) 0x41 0 0 100000 digit 2 plane p1 blank digit (0x20) 0x42 0 0 100000 digit 3 plane p1 blank digit (0x20) 0x43 0 0 100000 table 6. initial power-up register status
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 13 global blink enable/disable (e data bit d3) format the e bit globally enables or disables the blink feature of the device (table 10). when blink is globally enabled, then the digit data in both planes p0 and p1 are used to control the display (table 11). when blink is globally disabled, then only the digit data in plane p0 is used to control the display. the digit data in plane p1 is ignored. global blink timing synchronization (t data bit d4) format by setting the t bit in multiple max6953s at the same time (or in quick succession), the blink timing can be synchronized across all the devices (table 12). note that the display multiplexing sequence is also reset, which might give rise to a one-time display flicker when the register is written. register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink function is disabled. p x r t 0 b x s blink function is enabled. p x r t 1 b x s table 10. global blink enable/disable (e data bit d3) format segment? bit setting in plane p1 segment? bit setting in plane p0 segment behavior 00 segment off 01 segment on only during the 1st half of each blink period 10 segment on only during the 2nd half of each blink period 11 segment on table 11. digit register mapping with blink globally enabled register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink timing counters are unaffected. p x r 0 e b x s blink timing counters are reset during the i 2 c acknowledge. pxr1ebxs table 12. global blink timing synchronization (t data bit d4) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 digit data for both planes p0 and p1 are unaffected. p x 0 t e b x s digit data for both planes p0 and p1 are cleared during i 2 c acknowledge. px1tebxs table 13. global clear digit data (r data bit d5) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 p1 blink phase 0 x r t e b x s p0 blink phase 1 x r t e b x s table 14. blink phase readback (p data bit d7) format
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 14 ______________________________________________________________________________________ global clear digit data (r data bit d5) format when global digit data clear is set, the digit data for both planes p0 and p1 for all digits are cleared during the acknowledge (table 13). blink phase readback (p data bit d7) format when the configuration register is read, the p bit reflects the state of the blink output pin at that time (table 14). character generator font mapping the font is a 5 ? 7 matrix comprising 104 characters in rom, and 24 user-definable characters. the selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. the most-signifi- cant bit, shown as x in the rom map, is zero to light leds as shown by the black segments in table 15, and 1 to display the inverse. the character map follows the arial font for 96 charac- ters in the range 0x0101000 through x1111111. the first 32 characters map the 24 user-definable positions (ram00 to ram23), plus eight extra common charac- ters in rom. user-defined fonts the 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in max6953's internal ram. the 120 user-definable font data entries are written and read through a single register, address 0x05. an autoincrementing font address pointer in the max6953 indirectly accesses the font data. the font address pointer can be written, setting one of 120 addresses between 0x00 and 0xf7, but cannot be read back. the font data is written to and read from max6953 indirect- ly, using this font address pointer. unused font loca- tions can be used as general-purpose scratch ram, bearing in mind that the font registers are only 7 bits wide, not 8. table 16 shows how the single user-defined font regis- ter 0x05 is used to set the font address pointer, write font data, and read font data. a read action always returns font data from the font address pointer position. a write action sets the 7-bit font address pointer if the msb is set, or writes 7-bit font data to the font address pointer position if the msb is clear. the font address pointer autoincrements after a valid access to the user-definable font data. auto- incrementing allows the 120 font data entries to be writ- ten and read back very quickly because the font point- er address need only be set once. when the last data location 0xf7 is written, the font address pointer autoin- crements to address 0x80. if the font address pointer is 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 x000 x001 x010 x011 x100 x101 x110 x111 ram00 ram01 ram02 ram03 ram04 ram05 ram06 ram07 msb lsb ram08 ram09 ram10 ram11 ram12 ram13 ram14 ram15 ram16 ram17 ram18 ram19 ram20 ram21 ram22 ram23 table 15. character map
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 15 set to an out-of-range address by writing data in the 0xf8 to 0xff range, then address 0x80 is set instead (table 17). table 18 shows the user-definable font pointer base addresses. table 19 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. table 20 shows the six sequential write commands required to set a max6953's font character ram02 with the data to display character 2 given in the font ram illustration above. multiplex clock and blink timing the osc pin can be fitted with capacitor c set to gnd (to use the internal rc multiplex oscillator), or driven by an external clock. the multiplex clock frequency deter- mines the multiplex scan rate and the blink timing. the display scan rate (the frequency that the complete four- digit display is updated) is calculated by dividing the frequency at osc by 5600. with osc at 4mhz, each digit row is enabled for 100?, and the display scan rate is 714.29hz. the on-chip oscillator may be accurate enough for applications using a single device. if an exact blink rate is required, use an external clock ranging between 1mhz and 8mhz to drive osc. the osc inputs of mul- tiple max6953s can be tied together to a common external clock to make the devices blink at the same rate. the relative blink phasing of multiple max6953s can be synchronized by setting the t bit in the configu- ration register for all the devices in quick succession (table 12). blink output the blink output pin indicates the blink phase, and is high during the p0 period and low during the p1 period. blink phase status can also be read back as the p bit in the configuration register (table 14). typical uses for this output are: to provide an interrupt to the processor so that seg- ment data can be changed synchronous to the blinking. for example, a clock application may have colon segments blinking every second between hours and minute digits, and the minute display is best changed in step with the colon segments. also, if the rising edge of blink is detected, there is half a blink period to change the p1 digit data. similarly, if the falling edge of blink is detected, the user has half a blink period to change the p0 digit data. if osc is driven with an accurate frequency, blink can be used as a seconds counter or similar. scan-limit register the scan-limit register sets how many monocolor digits are displayed, either two or four. a bicolor digit is con- nected as two monocolor digits (table 21). address code (hex) register data i 2 c read or write function 0x05 0x00?x7f read read 7-bit user-definable font data entry from current font address. msb of the register data is clear. font address pointer is incremented after the read. 0x05 0x00?x7f write write 7-bit user-definable font data entry to current font address. font address pointer is incremented after the write. 0x05 0x80?xff write write font address pointer with the register data. table 16. memory mapping of user-defined font register 0x05 font pointer address action 0x80 to 0xf6 valid range to set the font address pointer. pointer autoincrements after a font data read or write, while pointer address remains in this range. 0xf7 font address resets to 0x80 after a font data read or write to this pointer address. 0xf8 to 0xff invalid range to set the font address pointer. pointer is set to 0x80 if address. table 17. font pointer address behavior
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 16 ______________________________________________________________________________________ digit 1 row 1 digit 1 row 2 digit 1 row 3 digit 1 row 4 digit 1 row 5 digit 1 row 6 digit 1 row 7 digit 3 row 1 digit 3 row 2 digit 3 row 3 digit 3 row 4 digit 3 row 5 digit 3 row 6 digit 3 row 7 digit 1 row 1 column driver pins o19-o23 digit 0 row 1 digit 0 row 2 digit 0 row 3 digit 0 row 4 digit 0 row 5 digit 0 row 6 digit 0 row 7 digit 2 row 1 digit 2 row 2 digit 2 row 3 digit 2 row 4 digit 2 row 5 digit 2 row 6 digit 2 row 7 digit 0 row 1 column driver pins o14-o18 digit 1 row 1's 100 s multiplex timeslot current source 1/16th 2/16th (min on) 3/16th 4/16th 5/16th 6/16th 7/16th 8/16th 9/16th 10/16th 11/16th 12/16th 13/16th 14/16th 15/16th 16/16th (max on) current source current source current source current source current source current source current source current source current source current source current source current source current source current source current source one complete 1.4ms multiplex cycle around 14 rows 100 s digit 1 column driver outputs pins o19-o23 high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z digits 0 and 1 row outputs pins o0?6 high-z low digits 2 and 3 row outputs pins o7?13 high-z high-z high-z minimum 6.25 s interdigit blanking interval start of next cycle figure 10. multiplex timing diagram (osc = 4mhz)
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 17 the multiplexing scheme drives digits 0 and 1 at the same time, then digits 2 and 3 at the same time. to increase the effective brightness of the displays, drive only two digits instead of four. by doing this, the aver- age segment current doubles, but also doubles the number of max6953s required to drive a given number of digits. because digit 1 is driven at the same time as digit 0 (and digit 3 is driven at the same time as digit 2), only 1 bit is used to set the scan limit. the bit is clear if one or two digits are to be driven, and set if three or four digits are to be driven (table 21). intensity registers display brightness is controlled digitally by four pulse- width modulators, one for each display digit. each digit is controlled by a nibble of one of the two intensity reg- isters, intensity10 and intensity32. the modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. the minimum interdigit blanking time is therefore 1/16 of a cycle. the maximum duty cycle is 15/16 (tables 23 and 24). no-op register a write to the no-op register is ignored. selecting external components r set and c set to set oscillator frequency and segment current the rc oscillator uses an external resistor r set and an external capacitor c set to set the oscillator frequency, f osc . the allowed range of f osc is 1mhz to 8mhz. r set also sets the peak segment current. the recom- mended values of r set and c set set the oscillator to register data font character address code (hex) register data (hex) d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x05 0x80 1 0 0 0 0 0 0 0 ram01 0x05 0x85 1 0 0 0 0 1 0 1 ram02 0x05 0x8a 1 0 0 0 1 0 1 0 ram03 0x05 0x8f 1 0 0 0 1 1 1 1 ram04 0x05 0x94 1 0 0 1 0 1 0 0 ram05 0x05 0x99 1 0 0 1 1 0 0 1 ram06 0x05 0x9e 1 0 0 1 1 1 1 0 ram07 0x05 0xa3 1 0 1 0 0 0 1 1 ram08 0x05 0xa8 1 0 1 0 1 0 0 0 ram09 0x05 0xad 1 0 1 0 1 1 0 1 ram10 0x05 0xb2 1 0 1 1 0 0 1 0 ram11 0x05 0xb7 1 0 1 1 0 1 1 1 ram12 0x05 0xbc 1 0 1 1 1 1 0 0 ram13 0x05 0xc1 1 1 0 0 0 0 0 1 ram14 0x05 0xc6 1 1 0 0 0 1 1 0 ram15 0x05 0xcb 1 1 0 0 1 0 1 1 ram16 0x05 0xd0 1 1 0 1 0 0 0 0 ram17 0x05 0xd5 1 1 0 1 0 1 0 1 ram18 0x05 0xda 1 1 0 1 1 0 1 0 ram19 0x05 0xdf 1 1 0 1 1 1 1 1 ram20 0x05 0xe4 1 1 1 0 0 1 0 0 ram21 0x05 0xe9 1 1 1 0 1 0 0 1 ram22 0x05 0xee 1 1 1 0 1 1 1 0 ram23 0x05 0xf3 1 1 1 1 0 0 1 1 table 18. user-definable font pointer base address table
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 18 ______________________________________________________________________________________ register data scan limit address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code display digits 0 and 1 only 0x03 x x x x x x x0 0xx0 display digits 0, 1, 2, and 3 0x03 x x x x x x x1 0xx1 table 21. scan-limit register format register data font character font address pointer address code (hex) font pointer address (hex) d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x00 0x05 0x80 0 0 1 1 1 1 1 0 ram00 0x01 0x05 0x81 0 1 0 1 000 1 ram00 0x02 0x05 0x82 0 1 00 1 00 1 ram00 0x03 0x05 0x83 0 1 000 1 0 1 ram00 0x04 0x05 0x84 0 0 1 1 1 1 1 0 ram01 0x05 0x05 0x85 0 0 0 0 0 0 0 0 ram01 0x06 0x05 0x86 0 1 0 000 1 0 ram01 0x07 0x05 0x87 0 1 1 1 1 1 1 1 ram01 0x08 0x05 0x88 0 1 0 00000 ram01 0x09 0x05 0x89 0 0 0 0 0 0 0 0 ram02 0x0a 0x05 0x8a 0 1 0 000 1 0 ram02 0x0b 0x05 0x8b 0 1 1 0000 1 ram02 0x0c 0x05 0x8c 0 1 0 1 000 1 ram02 0x0d 0x05 0x8d 0 1 00 1 00 1 ram02 0x0e 0x05 0x8e 0 1 000 1 1 0 table 19. user-definable character storage example address code (hex) register data (hex) action being performed 0x05 0x8a set font address pointer to the base address of font character ram02. 0x05 0x42 1st 7 bits of data: 1000010 goes to font address 0x8a; pointer then autoincrements to address 0x8b. 0x05 0x61 2nd 7 bits of data: 1100001 goes to font address 0x8b; pointer then autoincrements to address 0x8c. 0x05 0x51 3rd 7 bits of data: 1010001 goes to font address 0x8c; pointer then autoincrements to address 0x8d. 0x05 0x49 4th 7 bits of data: 1001001 goes to font address 0x8d; pointer then autoincrements to address 0x8e. 0x05 0x46 5th 7 bits of data: 1000110 goes to font address 0x8e; pointer then autoincrements to address 0x8f. table 20. setting a font character to ram example
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 19 4mhz, which makes the blink frequencies 0.5hz selec- table between 1hz. the recommended value of r set also sets the peak current to 40ma, which makes the segment current adjustable from 2.5ma to 37.5ma in 2.5ma steps: i seg = k i / r set ma f osc = k f / (r set ? (c set + c stray )) mhz where: k i = 2144 k f = 6003 r set = external resistor in k ? c set = external capacitor in pf c stray = stray capacitance from osc pin to gnd in pf, typically 2pf the recommended value of r set is 53.6k ? and the recommended value of c set is 26pf. the recommended value of r set is the minimum allowed value since it sets the display driver to the maximum allowed segment current. r set can be set to a higher value to set the segment current to a lower peak value where desired. the user must also ensure that the peak current specifications of the leds con- nected to the driver are not exceeded. the effective value of c set includes not only the actual external capacitor used, but also the stray capacitance from osc to gnd. this capacitance is usually in the 1pf to 5pf range, depending on the layout used. display-test register the display-test register switches the drivers between one of two modes: normal and display test. display-test mode turns all leds on by overriding, but not altering, all control and digit registers (including the shutdown register). in display-test mode, eight digits are scanned and the duty cycle is 7/16 (half power). table 22 lists the display-test register format. applications information choosing supply voltage to minimize power dissipation the max6953 drives a peak current of 40ma into leds with a 2.4v forward-voltage drop when operated from a supply voltage of at least 3.0v. the minimum voltage drop across the internal led drivers is therefore (3.0v - 2.4v) = 0.6v. if a higher supply voltage is used, the dri- ver absorbs a higher voltage, and the driver? power dissipation increases accordingly. however, if the leds used have a higher forward voltage drop than 2.4v, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.6v headroom. the voltage drop across the drivers with a nominal 5v supply (5.0v - 2.4v) = 2.6v is nearly 3 times the drop across the drivers with a nominal 3.3v supply (3.3v - 2.4v) = 0.9v. in most systems, consumption is an important design criterion, and the max6953 should be operated from the system? 3.3v nominal supply. in other designs, the lowest supply voltage may be 5v. the issue now is to ensure that the dissipation limit for the max6953 is not exceeded. this can be achieved by inserting a series resistor in the supply to the max6953, ensuring that the supply decoupling capaci- tors are still on the max6953 side of the resistor. for example, consider the requirement that the minimum supply voltage to a max6953 must be 3.0v, and the input supply range is 5v ?%. maximum supply current is: 15ma + (40ma ? 10) = 415ma minimum input supply voltage is 4.75v. maximum series resistor value is: (4.75v - 3.0v) / 0.415a = 4.22 ? we choose 3.3 ? ?%. worst-case resistor dissipation is at maximum toleranced resistance, i.e., (0.415a) 2 ? (3.3 ? x 1.05) = 0.577w. we choose a 1w resistor rat- ing. the maximum max6953 supply voltage is at maxi- mum input supply voltage and minimum toleranced resistance, i.e., 5.25v - (0.415a ? 3.3 ? ? 0.95) = 3.95v. register data mode address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 normal operation 0x07 x x x x x x x 0 display test 0x07 x x x x x x x 1 table 22. display-test register format
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 20 ______________________________________________________________________________________ duty cycle typical segment current (ma) address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) 2.5 0x01, 0x02 0000 0xx0 2/16 5 0x01, 0x02 0001 0xx1 3/16 7.5 0x01, 0x02 0010 0xx2 4/16 10 0x01, 0x02 0011 0xx3 5/16 12.5 0x01, 0x02 0100 0xx4 6/16 15 0x01, 0x02 0101 0xx5 7/16 17.5 0x01, 0x02 0110 0xx6 8/16 20 0x01, 0x02 0111 0xx7 9/16 22.5 0x01, 0x02 1000 0xx8 10/16 25 0x01, 0x02 1001 0xx9 11/16 27.5 0x01, 0x02 1010 0xxa 12/16 30 0x01, 0x02 1011 0xxb 13/16 32.5 0x01, 0x02 1100 0xxc 14/16 35 0x01, 0x02 1101 0xxd 15/16 37.5 0x01, 0x02 1110 0xxe 15/16 (max on) 37.5 0x01, 0x02 see table 24. 1111 0xxf table 23. intensity register format for digit 0 (address 0x01) and digit 2 (address 0x02) duty cycle typical segment current (ma) address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) 2.5 0x01, 0x02 0 000 0x0x 2/16 5 0x01, 0x02 0 001 0x1x 3/16 7.5 0x01, 0x02 0 010 0x2x 4/16 10 0x01, 0x02 0 011 0x3x 5/16 12.5 0x01, 0x02 0 100 0x4x 6/16 15 0x01, 0x02 0 101 0x5x 7/16 17.5 0x01, 0x02 0 110 0x6x 8/16 20 0x01, 0x02 0 111 0x7x 9/16 22.5 0x01, 0x02 1 000 0x8x 10/16 25 0x01, 0x02 1 001 0x9x 11/16 27.5 0x01, 0x02 1 010 0xax 12/16 30 0x01, 0x02 1 011 0xbx 13/16 32.5 0x01, 0x02 1 100 0xcx 14/16 35 0x01, 0x02 1 101 0xdx 15/16 37.5 0x01, 0x02 1 110 0xex 15/16 (max on) 37.5 0x01, 0x02 1 111 see table 23. 0xfx table 24. intensity register format for digit 1 (address 0x01) and digit 3 (address 0x02)
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 21 low-voltage operation the max6953 works over the 2.7v to 5.5v supply range. the minimum useful supply voltage is deter- mined by the forward-voltage drop of the leds at the peak current i seg , plus the 0.6v headroom required by the driver output stages. the max6953 correctly regu- lates i seg with a supply voltage above this minimum voltage. if the supply drops below this minimum volt- age, the driver output stages may brown out, and be unable to regulate the current correctly. as the supply voltage drops further, the led segment drive current becomes effectively limited by the output driver's on- resistance, and the led drive current drops. the char- acteristics of each individual led in a 5 ? 7 matrix digit are well matched, so the result is that the display inten- sity dims uniformly as supply voltage drops out of regu- lation and beyond. the max6953 operates down to 2v supply voltage (although most displays are very dim at this voltage), providing that the max6953 is powered up initially to at least 2.7v to trigger the device's internal reset, and also that the i 2 c interface is constrained to 100kbps. computing power dissipation the upper limit for power dissipation (pd) for the max6953 is determined from the following equation: p d = (v+ ? 15ma) + (v+ - v led ) (duty ? i seg ? n) where: v+ = supply voltage duty = duty cycle set by intensity register n = number of segments driven (worst case is 10) v led = led forward voltage i seg = segment current set by r set p d = power dissipation, in mw if currents are in ma dissipation example: i seg = 40ma, n = 10, duty = 15 / 16, v led = 2.4v at 40ma, v+ = 3.6v p d = 3.6v (15ma) + (3.6v - 2.4v) (15 / 16 ? 40ma ? 10) = 0.504w thus, for a 36-pin ssop package (t ja = 1 / 0.0118 = +85?/w from operating ratings), the maximum allowed ambient temperature t a is given by: t j(max) = t a + (p d ? t ja ) = +150? = t a + (0.504 ? +85?/w) so t a = +107?. thus, the part can be operated safely at a maximum package temperature of +85?. power supplies the max6953 operates from a single 2.7v to 5.5v power supply. bypass the power supply to gnd with a 0.1? capacitor as close to the device as possible. add a 47? capacitor if the max6953 is not close to the board's input bulk decoupling capacitor. board layout when designing a board, use the following guidelines: 1) the r set connection to the iset pin is a high- impedance node, and sensitive to layout. place r set right next to the iset pin and route r set directly to these pins with very short tracks. 2) ensure that the track from the ground end of r set routes directly to gnd pin 19 (pdip package) or gnd pin 17 (ssop package), and that this track is not used as part of any other ground connection. chip information transistor count: 44,078 process: cmos
max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 22 ______________________________________________________________________________________ pin configurations 40 o23 o22 o21 v+ v+ v+ o20 o19 o18 o17 o16 o15 o14 o13 o12 n.c. scl sda ad0 osc 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 o0 o1 o2 gnd gnd gnd o3 o4 o5 o6 o7 o8 o9 o10 o11 n.c. iset ad1 gnd blink top view max6953 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 pdip 20 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 o23 o22 o21 v+ v+ o20 o12 o19 o18 o17 o16 o15 o14 o13 o11 o10 o9 o8 o7 o6 o5 o4 o3 gnd gnd o2 o1 o0 ssop max6953 22 21 20 19 15 16 17 18 osc scl sda ad0 blink gnd ad1 iset
package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) max6953 2-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 23 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. ssop.eps package outline, 36l ssop, 0.80 mm pitch 1 1 21-0040 e rev. document control no. approval proprietary information title: front view max 0.011 0.104 0.017 0.299 0.013 inches 0.291 0.009 e c dim 0.012 0.004 b a1 min 0.096 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.30 2.44 min 0.44 0.29 max 2.65 0.040 0.020 l 0.51 1.02 h 0.414 0.398 10.11 10.51 e 0.0315 bsc 0.80 bsc d 0.612 0.598 15.20 15.55 h e a1 a d e b 0 -8 l c top view side view 1 36

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